The present invention relates in general to a computer system and pertains more particularly to a system that is constructed quite inexpensively employing on the order of 80 integrated circuits and having the capability of communicating with a number of port devices.
One object of the present invention is to provide an improved computer system having manual reset means for controlling the central processing unit.
Another object of the present invention is to provide an improved addressing scheme for the random access memory of the system.
A further object of the present invention is to provide a computer system that has the capability of a video output that may be either alpha numeric or graphic.
Still another object of the present invention is to provide a computer system having a video output for providing different size characters. In accordance with the present invention the output can be controlled so as to display either 32 characters per line or 64 characters per line.
Another object of the present invention is to provide an improved computer system for providing a chain control of the video RAMs or alternatively control directly from the data bus of the CPU.
Another object of the present invention is to provide a computer system having the capability of graphic display. In accordance with the invention, the display field is demarcated into rectangular segments with each segment in turn sectioned into, for example, 6 parts which are individually selectable by data bus information.
Still another object of the present invention is to provide an improved computer system having a novel keyboard entry scheme.
A further object of the present invention is to provide an improved computer system having a novel port control specially useful with a port device such as a tape recorder/player.
To accomplish the foregoing and other objects of this invention, there is provided a computer system including a central processing unit, means for storing instructions for the central processing unit disclosed as a read-only memory (ROM), random access memory means for storing data, keyboard means for entering data into the computer system, and display means disclosed in the form of a conventional CRT television display. Connections from the central processing unit, (CPU) include control lines, a plurality of data lines, forming a data bus and a plurality of address lines, forming an address bus. The data lines are bi-directional whereas the address lines are uni-directional. The CPU interrogates other components of the computer system by way of the address bus to indicate where the data it is looking for is located. The data bus is the means of comunication for data both to and from the CPU. The ROM contains the instructions for the CPU indicating to the CPU what to do, how to carry out the instruction, and where to put the data after the instruction is completed. The CPU essentially looks to the ROM for instructions and then follows the instructions of the ROM. In all communications, the CPU applies address locations to both the ROM, RAM, and keyboard. However, address decoding determines which of these actual memories the CPU is looking for. In the system of this invention only the CPU communicates with all other sections. For example, data is to be transferred from the ROM into the RAM, the transfer is accomplished by way of the CPU. The keyboard means enables entry of instructions and data to the CPU. The system of this invention also includes a video random access memory (video RAM) which couples to a video processing section which in turn couples to a video output terminal or monitor such as a television receiver. Data in the video RAM is automatically displayed on the monitor.
In accordance with one feature of the present invention, there is provided a reset switch which is operable by the operator of the computer system to reset the system by forcing the CPU to a known address. This reset switch resets the microprocessor when it is lost. At power-up the microprocessor (CPU) is reset with instructions being initiated from the ROM starting at an initial address. If at a later time the CPU becomes lost for any reason in accordance with this invention there is provided a reset switch for resetting the CPU starting with execution of instructions from a predetermined address in the ROM. In the disclosed embodiment, this predetermined address is .0..0.66, The reset switch is operable at the conventional interrupt input to the microprocesser. The reset switch preferably has an R-C circuit associated therewith which is charged when the reset switch is released to permit the CPU to continue operation.
In accordance with another feature of the present invention, there is provided a means for readily selecting different capacity memories especially with regard to the random access memory of the computer system. In this regard the system of the present invention employs an address decoder for ROM/RAM selection. The address decoder is responsive to an address code from the central processing unit for providing separate outputs, some of which at least correspond to different coded inputs representative of different capacity memories. At the output of the address decoder, there is a selection means for selecting different outputs from the address decoder to provide a memory enable signal. The address decoder in accordance with the present invention preferably decodes the higher order address lines, specifically four such lines, with the output of the decoder providing up to 8 output signals, only one of which at a time is active. The selection means preferably includes a selection shunt means having input terminals coupling to the address decoder and with some of its output terminals commonly tied to provide the memory enable signal. One section of the shunt preferably contains 4 shorting bars, commonly tied at their output terminals. For a 4K memory capacity, one bar is shorted, for 8K, two bars are shorted, for 12K, three bars are shorted, and for 16K, all four bars are shorted. In the disclosed embodiment this means that the enabling signal for the random access memory is active all the way from address 4.0..0..0. to address FFFF.
In accordance with another feature of the present invention the random access memory uses a multiplexing scheme to input two partial addresses into the memory which together define one particular storage address. The internal logic in the RAM interprets two parts of the address code to provide one address typically with a total of 14 bits. One portion of the address is defined as a row address select while the other portion is defined as a column address select with a multiplexing signal being defined between these two address selections. Preferably there is also provided a selection means associated with the addressing of the RAMs which may be in the form of a shunt for directing different signals to the input enable for the memories. For a smaller capacity memory such as a 4K memory, a memory enable signal is always present, however, for a larger capacity memory such as a 16K memory, the shunt is selected under control of the multiplexing signal to provide different address line signals to the enable input of the memory. In this way the RAMs can easily be operated at different memory capacities depending upon the capacity desired.
In accordance with another feature of the present invention the computer system has the capability of changing the format of characters on the display to, for example, either 64 characters per line or 32 characters per line. In the disclosed embodiment, the display has 16 character lines and thus for a line containing 64 characters, there are thus 1024 character locations in the video RAM that are to be accessed. In the alternate format, the characters appear twice as large with 32 characters per line and thus there are only 512 video RAM locations that are to be accessed. The system includes a video RAM for the storage of character codes preferably in an ASCII code which may be interpreted as either an alpha numeric character or a graphic symbol in accordance with another feature of the present invention. The video RAM is addressed to take one code at a time from storage to a latch which in turn couples to a character generator for receiving the character code. The character generator decodes the input code and in accordance with a fan-line count, generates dot signals just stored in a shift register to be shifted out, one dot at a time for forming one or a line or a number of lines forming the character. The data is shifted out of the shift register by means of a clock signal referred to herein as a shift signal. This signal is controlled in at least two different manners for providing different video signals. In the disclosed embodiment the control is provided so as to give a format of either 32 characters per line or 64 characters per line. In accordance with the invention there is a basic clock signal which generates the shift signal. For the 32-character format, the shift signal is at one half the clock frequency whereas for the 64-character format the shift signal is at the clock frequency.
In accordance with another feature of the invention, the computer system provides for two different types of formats, including an alpha numeric format and a graphic format. Although there are two different formats, the same basic data stored in the video memory is used for the generation of both formats. In this regard, there is thus provided in the system a video code storage means which also includes storage of preferably one bit of information for determining whether the final format is alpha numeric or graphic. This system also includes a character generator means for receiving the video codes, one code at a time, and a graphic generator means which also receives the video codes, one code at a time. Preferably, there is a common latch circuit which has its output couple in common to both the character generator means and the graphic generator. Also, preferably at the output of these generators there are provided shift registers, one for each generator means. The shift registers convert the dot patterns from the generator means into a serial signal. This signal is coupled to the output video mixing circuit. Finally, in accordance with this feature, the system includes a means responsive to the state of the video format type signal for enabling either the character generator or the graphic generator. This latter means preferably comprises a gate means responsive to the state of certain bits forming each video code.
In accordance with still another feature of the present invention, there is provided the capability in accordance with the computer system of this invention of interpreting codes stored in a video memory either as a graphic display or as an alpha numeric display. In accordance with the alpha numeric display, as previously mention, there are 1024 character locations, with each location being defined by a 12.times.6 rectangle in accordance with the graphic display of th present invention, this rectangle, rather than being formed into a character is subdivided into a plurality of smaller rectangles such as six smaller rectangles to provide a basic graphic cell. This cell is the smallest area of graphic information that can be selectively displayed on the screen. Each cell is four scan lines hgh and three dots wide in the disclosed embodiment. Thus, in accordance with this feature of the invention there is provided a video code storage means for storing a plurality of codes with one code at a time being presented to a graphic cell generating means. A vertical address is provided preferably in the form of two bits also coupled to the graphic generating means. The graphic generator is responsive to both the vertical address and the video code for providing separately formed cells over the graphic area. This graphic generator is preferably in the form of a selector circuit responsive to both the vertical address and the state of certain bits defining the video code for determining the state of the cells in a horizontal direction.
In accordance with another important feature of the present invention there is provided an improved keyboard scheme, one that is relatively simple in construction and which is readily adapted to a simplified software scheme. In accordance with this feature, the keyboard comprises a plurality of keys arranged in a matrix having input lines depicted as horizontal lines formed in a first group, and output lines disclosed as vertical lines in a second group. The address lines coupled from the central processing unit, couple respectively to the input lines of the first group while the output lines tie to the data bus which also communicates with the central processing unit. The matrix is arranged so that when a switch is closed, there is essentially a connection between a horizontal common line and a vertical common line. When the keyboard enabling signal from the CPU is provided, essentially at the same time the address lines are all brought to a like state, such as a high state. If the output signal is detected on one of the data lines, this indicates to the central processing unit that there has been a key pressed on the keyboard. The central processing unit is essentially always in readiness for a keyboard detection when in the keyboard enable mode. Once the central processing unit makes this detection, then under control of the ROM, the address lines are scanned, one-by-one until the proper data line has been detected. In this way, a first detection on a data line represents one vertical location on the keyboard matrix while a detection at a later time identifies the horizontal position on the matrix, thus identifying one and only one key. After identifying the output, the ROM instructs the CPU to generate the ASCII code for that particular key.
Another feature of the present invention is the provision for an output/input port device which is preferably in the form of a taper recorder/player. The tape recorder is operable as both an input and output port device. In the output mode there is a recording of data on the tape. In this connection, the signals on the data line also control the motor of the recorder. In the input mode data is transferred from the tape recorder to the central processing unit. In accordance with this feature of the invention the data lines which may comprise six separate lines couple to the recorder and may be provided in two groups. In the preferred embodiment, in the input mode data is taken from the recorder onto a single data line. In the output mode in the disclosed embodiment there are four input data lines, one of which provides the mode select signal, another of which controls the motor and the two remaining ones of which are used to provide signals for recording data on the recorder tape.